1. Field of the Invention
The present invention generally relates to a semiconductor memory device and a method of testing the same, and more particularly, to a semiconductor memory device including a test circuit measuring a time period from a first timing of input of a command signal to a second timing to allow input of the next command signal and a method of testing the same.
Priority is claimed on Japanese Patent Application No. 2009-23906, filed Feb. 4, 2009, the content of which is incorporated herein by reference.
2. Description of the Related Art
In recent years, in order to meet the demand for high-speed data write/read processes with an increase in the speed of a clock that is input from outside, semiconductor memory devices have been required to reduce the time period from the first timing of input of a command signal to the second timing to allow input of the next command signal.
In order to ensure the reliability of the semiconductor memory device, it is necessary to perform a test under conditions of a shortened time period from the first timing of input of a command signal to the second timing to allow input of the next command signal. The test will be taken place before the shipment of the semiconductor memory device.
Japanese Unexamined Patent Applications, First Publications, Nos. JP-A-2003-346497 and JP-A-11-025695 disclose semiconductor memory devices including test circuits performing the above-mentioned test.
Japanese Unexamined Patent Application, First Publication, No. JP-A-2003-346497 discloses tRCD measurement which is a measurement for the time period from the input of an ACT command to the input of a READ command or a WRITE command. The tRCD measurement is an example of the tests for measuring the characteristics of the semiconductor memory device. JP-A-2003-346497 discloses that the tRCD measurement is limited by a time margin such as an address setup time and a hold time, which is necessary to shift an address input from a row address input to a column address input. Thus, the tRCD e measurement can not he accurately performed on the basis of the characteristics of the internal circuit.
Japanese Unexamined Patent Application, First Publication, No. JP-A-2003-346497 discloses that in order to solve the above-mentioned problem, a row address is kept in the semiconductor memory device in advance before the ACT command is input so that it is not necessary to shift the address during the time period from the input of the ACT command to the input of the READ command or the WRITE command input.
Japanese Unexamined Patent Application, First Publication, No. JP-A-11-025695 discloses that a semiconductor memory device generates an internal command signal that is asynchronous with an external clock and the semiconductor memory device includes an internal circuit which is tested at a high frequency that is equal to that of the external clock on the basis of the internal command signal, without being synchronized with the external clock.